1. Field
Apparatuses and methods consistent with exemplary embodiments relate to signal processing, and more particularly, to a digital duty cycle correction circuit.
2. Description of the Related Art
As an electronic system becomes smaller and has a higher operating speed, a semiconductor device included in the electronic system also becomes smaller and has a higher operating speed. Typically, the semiconductor device transceives data to and/or from another semiconductor device in synchronization with a clock signal. As data input/output (I/O) speed required by the semiconductor device increases, a double data rate (DDR) method may be used. In the DDR method, the data I/O speed is doubled in a way that data are respectively transferred at both a rising edge and a falling edge of a clock signal, and thus a duty cycle of the clock signal, which indicates a ratio of a logic low level interval of the clock signal to a logic high level interval of the clock signal, is one of factors for improving performance of the semiconductor device.